Corrected from:
PLC Designer V3.24
Behavior of the new version:
If a standard project is created for the 3200C controller and then compiled unchanged, no error message appears. The cycle time of the bus cycle task matches the DC master cycle time.
Description of the behaviour:
During compilation the following compiler warning occurs, although the cycle time on the tab card of the EtherCAT Master and the interval in the MainTask of the task configuration are at the same value:
EtherCAT Master : The cycle time of the bus cycle task does not match the DC master cycle time. DC may not work!
Under what conditions does the behaviour occur?
The warning is issued if a standard project for the 3200C controller is created and then compiled unchanged.
Affected products:
PLC Designer as of V3.18
Short-term measures:
Change the value for the cycle time on the tab card of the EtherCAT Master and enter the original value again. If a new compilation is performed now, the warning no longer appears.
Evaluation/Recommendations:
If the two above values for the cycle time are the same, the warning can be ignored or canceled as described above. The project will function correctly even if the warning is issued.
Automatic Translation
